CPUs by George Hernandez

Intro

CPU (Central Processing Unit). A CPU is the core of a computer, i.e. the processor, the ALU (Arithmetic Logic Unit), and the internal memory. It is composed of the main silicon chips of the computer which do the actual processing, as opposed to merely supporting functions like RAM or controlling peripherals. The processor itself is often referred to as the CPU.

The CPU takes data from the RAM and input devices. The CPU takes two kinds of data:
1. Instructions. The jobs (commands, data processing orders). EG: A Print command.
2. User Data. The content (input data) that the instructions work on. EG: An image.
The CPU then process the data.
The CPU then outputs the data to the RAM. The RAM communicates with the and I/O (input/output) devices.

The system bus (FSB, Front Side Bus) is the data throughput between the CPU and the RAM.

Applications usually know how to give instructions to a family or sub-family of CPUs (EG: x86 CPUs). The outer layer of a CPU can then translate (decode) the application instruction into internal instructions that that particular member of that family can understand (EG: 80286 CPU).

This layering enables some degree of backwards compatibility and encapsulation. However each generation of a family added new instructions (amongst other changes) so that some applications required the new generation to work. EG: +26 instructions with the 80386, +6 with the 80486, and +8 with the Pentium.

There are different groups of internal instructions, which is outside of the family "grouping". Here they are in chronological order.

CISC (Complex Instruction Set Computer). The instructions varied in length (8-120 b), with 1 instruction per word (chunk of data received).
RISC (Reduced Instruction Set Computer). The instructions were all the same size (EG: 32 b in Pentium), with 1 instruction per word.
VLIW (Very Long Instruction Word). The instructions were all the same size, but with multiple instructions per word.

From the 80386DX and on, all CPUs have FPUs (Floating Point Unit processors) built in to help deal with non-whole numbers.

The clock speed (clock frequency) of a CPU refers to the number of clock ticks per second, hence this is usually measured in MHz. The clock ticks is tied to a crystal on the CPU and basically the CPU does something with each clock tick. The clock speed is one of the most common measure for the power of a CPU.

The internal clock speed (inside the CPU) could run higher than the external clock speed because of electromagnetic noise on the system bus or limitations on the RAM MHz. Clock factoring (clock doubling) is when the internal MHz is greater than the external MHz. Variations on the clock factor was the primary reason for the x486 variations.

Because of clock factoring, caches have been used to buffer data or store it temporarily since the 4th generation.

L1 cache (internal) is internal to the CPU.
L2 cache (external) is between the CPU and the RAM.
L3 cache (processor external) is between multiple processors in a NUMA system.

The register (data width) refers to how many bits the CPU can handle simultaneously.

internal data width. How many bits the CPU can process simultaneously.
external data width. How many bits the CPU can receive simultaneously.

Since the 5th generation some CPUs have enabled more pipelines (parallel processing) within the CPU so more instructions can be executed per clock tick.

Generations

Here are the CPUs that are compatible with the UNIX, DOS, and Windows OSes.

PC Generation	CPUs (usu. by Intel)	Year	Transistors	Basic Stats	Notes
0th	4004	1971	--
1st	8086	1978	29,000	0.5 MIPS 5-10 MHz.	8087 FPU. 16 b register. 16 b bus.
1st	8088	1979		0.5 MIPS 5-8 MHz.	The IBM PC and PC/XT.
2nd	80286	1984	134,000	1.5 MIPS 8-12 MHz.	The AT. 80287 FPU. Virtual memory. 16 MB address space.
3rd	80386				80387 FPU. 32 b register.
	80386DX	1985	275,000	10 MIPS 16-33 MHz.	FPU built in. Multi tasking. 4 GB address space.
	80386SX	1988		2.5 MIPS 16 b bus 16-33 MHz	No FPU.
	80386SL	1990		5 MIPS 32 b bus 20-25 MHz	32 b bus. Better power management.
4th	80486DX	1989		30 MIPS 25-50 MHz	8 KB L1. Coprocessor. Pipelining.
	80486SX	1991		20 MIPS 16-33 MHz	Like DX but without the coprocessor.
	80486DX2	1992		50 MIPS 50-66 MHz	8 KB L1.
	80486DX4	1994	1,200,000	70 MIPS 75-100 MHz	16 KB L1.
5th	Pentium (80586)	1993	3,100,000	125 MIPS 60-200 MHz	64 b bus.
	6x86 by Cyrix	1996
	K5 by AMD	1996
	WinChip C6 by IDT	1997	3,500,000
5th +	Pentium MMX	1997	4,500,000	166-200 MHz	32 KB L1.
	6x86MX by IBM/Cyrix	1997	6,000,000
	WinChip2 3D by IDT	1998	6,000,000
6th	Pentium Pro (80686)	1995	5,500,000	150-200 MHz	16 KB L1 and 256 KB L2. Socket 8.
	K6 by AMD	1997	8,800,000		64 KB L1.
	Pentium II	1997	7,500,000	233-333 MHz	32 KB L1. Slot 1.
	K6-2 by AMD	1998	9,300,000		64 KB L1.
6th +	Mobile Pentium II		7,400,000
	Mobile Celeron	1998/06	18,900,000		32 KB L1 + 128 KB L2.
	Xeon	1998		400+ MHz	Slot 2 form factor for data transfer between the CPU and L2.
	Pentium III	1999	19,300,000	450+ MHz	32 KB L1.
	K6-3 by AMD				64 KB L1 + 256 KB L2.
	Pentium III CuMine	1999	28,000,000		32 KB L1 + 256 KB L2.
7th	K7 Athlon by AMD	1999	22,000,000		128 KB L1.
	K7 Athlon Thunderbird by AMD	2000	37,000,000		128 KB L1 + 256 KB L2.
	Pentium 4 "Meced"	2001	42,000,000		VLIW.
8th	Opteron "SledgeHammer" by AMD				64 b register. HyperTransport.
	Itanium "Madison"	2003-05			Hyper-Threading.
	Itanium 2 "Deefield"	2003-09			Lower voltage and size.

Here are CPUs compatible with the Macintosh OS, with the later ones also UNIX OS capable.

CPU	Year	Notes
6800	1984
68020	1986
68030	1987
68040 & 68LC040	1992
68060	1993
Power PC 601	1994	RISC
Power PC 603 & 603e	1995
Power PC 604 & 604e	1996
Power PC G3 740 & 750	1997
Power PC G4	1999	iMacs, Xserve. 64 b register.

CPUs

Intro

Generations

Links